AMD Zen 6 Architecture Rumored To Power EPYC Venice Server CPUs: Over 200 Cores, Completely Redesigned L2/L3 Cache & HBM SKUs

The successor to AMD's EPYC Turin CPUs which will feature Zen 5 cores is rumored to be called EPYC Venice and will feature Zen 6 architecture, reports Moore's Law is Dead.

AMD EPYC Venice Server CPUs Rumored To Feature Over 200 Zen 6 Cores With Redesigned L2/L3 Cache & HBM SKUs

While the details are quite vague at the moment considering this product isn't expected to launch till 2025+, it looks like MLID got his hands on very early details regarding the codename and AMD's marketing has come up with 'Venice' for its next-generation EPYC lineup. Named after the capital of the Veneto region in northeastern Italy, the EPYC Venice lineup is expected to be a huge update for servers.

Some details that are shared include references to the AMD Zen 6 cores though it is not known if the red team will continue with its Zen naming scheme beyond 2025 or move to something else. The server segment will continue with the EPYC naming convention. It is said that Zen 6 or the x86 architecture after Zen 5 will make use of a very hybrid core design approach and can offer over 200 cores (a conservative estimate) with rumors of up to 384 cores per socket. There's no mention if the CPU will be compatible with the SP5 platform but it looks like Turin and its follow-up on Zen 5C might be the last EPYC chips for the upcoming platform. The SP5 socket will last till 2025 which is a good timeframe to provide an update.

As for the upgrades in the architecture itself, the leaker also stated that the AMD is expected to completely redesign the L2 and L3 cache system. The Infinity Cache architecture will also see a major change. Also, HBM will become the standard across most of the lineup and the memory standard will play a huge role in next-generation EPYC CPUs. The on-board HBM hybrid design integrated within EPYC can be used to scale IPC within the same core count. One interesting and key detail is that Tom also expects Zen 5-based EPYC offerings to be amongst the first AMD EPYC server products to feature HBM designs while EPYC Venice will standardize it across multiple SKUs.

In the end, while all of this sounds great, one should remember we are talking about products that launch 3-4 years from now and a lot can change in the meantime. But it looks like EPYC Venice from AMD might indeed be a thing and we can't wait to see it in action a few years from now!

AMD EPYC CPU Families:

Family Name	AMD EPYC Naples	AMD EPYC Rome	AMD EPYC Milan	AMD EPYC Milan-X	AMD EPYC Genoa	AMD EPYC Bergamo	AMD EPYC Turin
Family Branding	EPYC 7001	EPYC 7002	EPYC 7003	EPYC 7003X?	EPYC 7004?	EPYC 7005?	EPYC 7006?
Family Launch	2017	2019	2021	2022	2022	2023	2024-2025?
CPU Architecture	Zen 1	Zen 2	Zen 3	Zen 3	Zen 4	Zen 4C	Zen 5
Process Node	14nm GloFo	7nm TSMC	7nm TSMC	7nm TSMC	5nm TSMC	5nm TSMC	3nm TSMC?
Platform Name	SP3	SP3	SP3	SP3	SP5	SP5	SP5
Socket	LGA 4094	LGA 4094	LGA 4094	LGA 4094	LGA 6096	LGA 6096	LGA 6096
Max Core Count	32	64	64	64	96	128	256
Max Thread Count	64	128	128	128	192	256	512
Max L3 Cache	64 MB	256 MB	256 MB	768 MB?	384 MB?	TBD	TBD
Chiplet Design	4 CCD's (2 CCX's per CCD)	8 CCD's (2 CCX's per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	TBD
Memory Support	DDR4-2666	DDR4-3200	DDR4-3200	DDR4-3200	DDR5-5200	DDR5-5600?	DDR5-6000?
Memory Channels	8 Channel	8 Channel	8 Channel	8 Channel	12 Channel	12 Channel	TBD
PCIe Gen Support	64 Gen 3	128 Gen 4	128 Gen 4	128 Gen 4	128 Gen 5	TBD	TBD
TDP Range	200W	280W	280W	280W	320W (cTDP 400W)	320W (cTDP 400W)	480W (cTDP 600W)

The post AMD Zen 6 Architecture Rumored To Power EPYC Venice Server CPUs: Over 200 Cores, Completely Redesigned L2/L3 Cache & HBM SKUs by Hassan Mujtaba appeared first on Wccftech.

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