Apple’s partnership with TSMC has propelled both companies to success. Courtesy of a close relationship with TSMC, Apple has delivered its A12X processor, which in turn has propelled the 2018 iPad Pro right alongside (and ahead of) low-powered notebooks. No other tech company has products with similar performance envelopes and form. Now, TSMC is looking at the future as it’s reported that the company will commence mass production of 3D chip packaging in 2021. TSMC’s WoW (Wafer-on-Wafer) packaging stems from the company’s InFO and CoWoS technologies. Take a look below for more details.
TSMC’s Joint-CEO Wei Zhejia Announces Mass Production of 5nm WoW Built Chips In 2021 After Completing World’s Frist 3D IC Package
The slowdown of Moore’s law and the complexities of advanced manufacturing process combined with the increasing computing needs of today has put tech companies in a conundrum. We’re seeing new technologies such as EUV for etching and GAAFET (Gate all around) for multigate devices present innovative solutions for the industry’s problems.
Now, as it gears up to produce processors using its 7FF+ process designs, Taiwanese fab TSMC has confirmed that the company will jump to 3D packaged chips in 2021. This shift will allow its customers to ‘stack’ multiple CPUs or GPUs on one another inside a single package – effectively doubling the number of transistors. To achieve this, TSMC will connect the two different die wafers using TSVs (Through Silicon Vias).
Stacked dies are common in the storage world, and TSMC’s WoW will apply this concept to computing silicon. TSMC has developed the technology in a partnership with California based Cadence Design Systems, and the technology is an extension of the company’s InFO (Integrated Fan-out) and CoWoS (Chip-on-Wafer-on-Substrate) 3D chip production techniques. The fab announced WoW last year, and now, it will start manufacturing with the new technology in 2021.
Looking at the timeframe, it’s likely that WoW will be used with 5nm. After 17nm, 5nm will allow companies such as Apple to cram as much as 10 Billion transistors on their SoCs, with a surface area similar to the current A12. TSMC will achieve the stacking by connecting the separate wafers on a 3D plane with TSVs (Through-Silicon-Vials). TSVs are essentially 10-micron holes that facilitate transfer between the two stacked chips. If we really do see WoW with 5nm, then the computing power available to developers for desktop and mobile applications will be immense, Love the 2018 iPad? You’ll get to witness the tablet’s computing power double but with a smaller footprint courtesy of 5nm. What more can we really wish for?
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