It’s a great time for mobile processors. Apple’s made progress in leaps and bounds on the front courtesy of TSMC’s lead in the semiconductor fabrication space. Qualcomm and Huawei aren’t too far behind either, with the only company showing slow progress being Samsung. Now, we’ve got more information on TSMC’s plans for its next-generation performance node. Take a look below for more details.
TSMC Has Successfully Completed Trial Production Of 5nm Wafers At Fab 18 – Company Expected To Enter Mass Production Next Year, With 5nm+
Last month we reported that TSMC had commenced risk production of its next-generation 5nm manufacturing process. The 5nm node is expected to provide an 80% increase in transistor density, a net 15% performance increase and a 40% reduction in surface area. This process will be used on several 2020 products, and if we’re lucky, Apple’s A14 will be right on time to utilize it when 5G starts to become mainstream.
We’re now hearing from Taiwan that TSMC’s trial production of 5nm (or the N5 as the company calls it) has finished. This means that the company should be ready to commence mass production when it sees fit, i.e, when orders start coming in. It’s an interesting report, as risk production for the process had commenced only last month, around the 5th of April. Looks like TSMC’ moving really fast with the node, but as this information is not from official sources, do take it with some salt for the time being.
The report from ITHome also expects that TSMC’s 5nm production will commence in the second quarter of 2020. Additionally, the report also provides details for TSMC’s plans for 5nm+. This node will boost performance by 7% at power consumption levels that are similar to 5nm or improve power consumption by 15% at performance levels similar to its predecessor. As per the information, trial production for 5nm+ will commence in the first quarter of next year, and mass production will commence in the year 2021, just in time for the company’s 3D stacked WoW (Wafer on Wafer) chips.
According to data from IBS Research, wafer price for 5nm will increase to $12,500/wafer as compared to $9,965 for 7nm. However, the process will allow for up to 10.5 billion transistors on an 85 mm2 die. But, this increase will be offset by a decreased NDPW (Net Die Per Wafer) value of 530.25 due to decreased yields from the process. Furthermore, TSMC’s stated parameters for 5nm aren’t in line with IRDS’ 2017 figures. Transistor gate and interconnect pitch for the process are set as 48 and 30nm respectively; which is more in line with the parameters for 7nm.
Thoughts? Let us know what you think in the comments section below and stay tuned. We’ll keep you updated on the latest.
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